A Scalable Multi-Processor Cache Coherence Protocol for Shared-Memory Architectures

International Journal of Computer Science and Technology Vol. 2, No. 6, June 2000 | pp. 41–48

DOI: 10.46882/2000/IJCST/000018

Research Article

Title: A Scalable Multi-Processor Cache Coherence Protocol for Shared-Memory Architectures

Names of Authors: Arthur Pendelton¹, Yuki Sato²

Authors’ Affiliations: ¹Department of Computer Architecture, University of Texas at Austin, USA; ²Graduate School of Engineering, Osaka University, Osaka, Japan.

Abstract:
Modern multi-processor systems face critical scalability and latency barriers when maintaining memory consistency across highly parallel compute environments. Standard directory-based cache coherence protocols induce extreme network message overheads and memory lookup bottlenecks as core counts expand. This paper develops an optimized, multi-level directory cache coherence protocol designed specifically for high-density, shared-memory processing arrays. The proposed protocol partitions directory records into localized clusters and uses a predictive sharing filter to restrict speculative coherence messages across the global interconnect bus. We evaluated our architectural engine using a cycle-accurate hardware simulator configured with up to 64 parallel processing cores executing diverse computational kernels. The experimental results show a 28.5% reduction in total cache-coherence message traffic and a 16.4% improvement in application execution speed relative to traditional MESI and MOESI baseline setups. The directory tracking memory footprint was lowered by 22.3%, ensuring that hardware scalability constraints are handled without imposing massive silicon area overheads within next-generation symmetric multiprocessing chips.

Keywords: Cache Coherence, Shared Memory, Parallel Architectures, Hardware Simulator, Multiprocessor Systems, Scalable Memory.

Manuscript Timeline: Received: March 02, 2000; Revised: April 08, 2000; Accepted: May 02, 2000; Published: June 18, 2000.

Citation: Pendelton, A., & Sato, Y. (2000). A Scalable Multi-Processor Cache Coherence Protocol for Shared-Memory Architectures. International Journal of Computer Science and Technology, 2(6), 41–48.

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