A Neuromorphic Hardware Accelerator for Low-Latency Spiking Neural Network Processing at the Network Edge

International Journal of Computer Science and Technology | Vol. 12, No. 5, May 2010 | pp. 33–40

DOI: 10.46882/2010/IJCST/000081

Article Type: Original Research Paper

Title: A Neuromorphic Hardware Accelerator for Low-Latency Spiking Neural Network Processing at the Network Edge

Names of Authors: Dr. Kenji Tanaka¹, Prof. Alex Yakovlev²

Authors’ Affiliations: ¹Department of Computer Science, Tokyo Institute of Technology, Tokyo, Japan; ²Department of Computing Science, Newcastle University, Newcastle upon Tyne, United Kingdom

Abstract: Abstract: Processing high-frequency temporal data streams using conventional deep learning architectures heavily strains the power and latency budgets of network edge installations. Spiking Neural Networks (SNNs) offer a biologically inspired, event-driven alternative, but standard Von Neumann processor configurations struggle to execute their asynchronous parallel dependencies efficiently. This paper presents a specialized neuromorphic hardware accelerator core tailored specifically for low-latency SNN operations. The architecture features an array of localized digital neurons that communicate via an address-event representation routing bus, bypassing global clock synchronization constraints. We fabricated the digital layout using a 65 nm standard CMOS process loop to analyze its physical performance. The empirical test benchmarks show that the accelerator achieves an operational processing latency of less than 4.5 ms when executing a 5-layer feedforward spiking network configuration. The average dynamic power consumption was limited to 12.8 mW, representing a 54.2% reduction relative to equivalent embedded graphics processor cores. The system maintains an inference classification accuracy threshold of 97.4% ±0.3% on complex spatiotemporal telemetry patterns, establishing a highly scalable, non-Von Neumann computing framework for localized autonomous robotics and intelligent cyber-physical monitoring systems.

Keywords: Neuromorphic hardware, spiking neural networks, hardware acceleration, edge computing, asynchronous logic, low-power design.

Manuscript Timeline: Received: March 22, 2010; Revised: April 25, 2010; Accepted: May 05, 2010; Published: May 17, 2010.

Citation: Tanaka, K., & Yakovlev, A. (2010). A Neuromorphic Hardware Accelerator for Low-Latency Spiking Neural Network Processing at the Network Edge. International Journal of Computer Science and Technology, 12(5), 33–40.

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