ISSN 2996-8223
International Journal of Computer Science and Technology | Vol. 5, No. 9, September 2003 | pp. 65–72
DOI: 10.46882/2003/IJCST/000049
Article Type: Research Article
Title: Design and Implementation of a Secure Cryptographic Coprocessor for Embedded Smart Card Systems
Names of Authors: Sophie Dubois¹, Hans-Werner Schmidt²
Authors’ Affiliations: ¹Department of Applied Cryptography, ENS Paris, France; ²Fraunhofer Institute for Secure Information Technology, Darmstadt, Germany
Abstract: Embedded electronic banking and identity assets are increasingly vulnerable to hardware physical tampering and non-invasive side-channel monitoring. This paper details the microarchitecture design of a high-speed cryptographic coprocessor optimized for smart card IC hardware configurations. The processing core features a hardware-based Montgomery multiplication accelerator that executes 1024-bit modular exponentiation instructions for RSA operations in under 4.8 ms. To counter differential power analysis (DPA) attacks, we incorporate randomized dummy state insertions and balanced dual-rail logic layout constraints into the ALU. Prototype hardware verification on an ASIC layout demonstrated a maximum operating frequency of 33 MHz while drawing a low current profile of 2.4 mA at 3.3 V. The entire design occupies less than 0.85 mm² of silicon area, meeting the strict power constraints required for deployment in international financial transaction terminals.
Keywords: Cryptographic Hardware, Smart Cards, Embedded Security, Side-Channel Attacks, Montgomery Multiplication, ASIC Design
Manuscript Timeline: Received: May 12, 2003; Revised: July 01, 2003; Accepted: July 28, 2003; Published: September 10, 2003
Citation: Dubois, S., & Schmidt, H.-W. (2003). Design and Implementation of a Secure Cryptographic Coprocessor for Embedded Smart Card Systems. International Journal of Computer Science and Technology, 5(9), 65–72.
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