International Journal of Computer Science and Technology

ISSN 2996-8223

International Journal of Computer Science and Technology | Vol. 8, No. 9, August 2006 | pp. 65–72

DOI: 10.46882/2006/IJCST/080924

Research Article

Title: An Automated Signature-Based Intrusion Detection Engine Using Parallel Hardware Automata

Names of Authors: Marcus Vance¹, Chen-Wei Hsu²

Authors’ Affiliations: ¹Department of Electrical and Electronic Engineering, University of Manchester, Manchester, UK; ²School of Computer Engineering, Nanyang Technological University, Singapore

Abstract:
Deep packet inspection (DPI) in high-speed networks requires high-performance pattern matching capabilities to identify malicious signatures in real time. This study introduces an automated signature-based intrusion detection engine implemented via parallel hardware finite automata. The architecture maps complex regular expression rules onto specialized memory-efficient non-deterministic finite automata (NFA) blocks that operate concurrently. The system was validated against a comprehensive signature database containing 2,500 distinct threat vectors. When compiled onto a modern FPGA target, the parallel execution pipeline successfully achieved a continuous processing throughput rate of 24.8 Gbps at a maximum clock frequency of f = 312.5 MHz. The hardware design reduces memory consumption parameters by 35.4% through a novel state-transition compression scheme, ensuring that line-rate network stream monitoring can be achieved with zero packet drop rates under peak traffic loads.

Keywords: Deep Packet Inspection, Finite Automata, FPGA Hardware, Intrusion Detection, Pattern Matching

Manuscript Timeline: Received May 14, 2006; Revised June 28, 2006; Accepted July 19, 2006; Published August 24, 2006

Citation: Vance, M., & Hsu, C. W. (2006). An Automated Signature-Based Intrusion Detection Engine Using Parallel Hardware Automata. International Journal of Computer Science and Technology, 8(9), 65–72.