International Journal of Computer Science and Technology

International Journal of Computer Science and Technology | Vol. 11, No. 2, February 2009 | pp. 9–16

DOI: 10.46882/2009/IJCST/000011

Article Type: Original Research Paper

Title: Optimized Energy-Aware Routing Protocol for Wireless Sensor Networks Using Genetic Algorithms

Names of Authors: John A. Benson¹, Mariam O. Al-Kouri²

Authors’ Affiliations: ¹Department of Computer Science, University of Excellence, London, UK; ²School of Information Technology, Global Tech Institute, Dubai, UAE

Abstract: Energy conservation remains a critical challenge in the deployment of Wireless Sensor Networks (WSNs) due to the limited battery capacity of sensor nodes. This paper presents an Optimized Energy-Aware Routing Protocol (OE-ARP) that minimizes total network energy consumption while maximizing throughput. We utilize a Genetic Algorithm (GA) approach to dynamically select optimal cluster heads based on residual energy, node density, and distance to the base station. Simulation results demonstrate that OE-ARP reduces energy dissipation by up to 28.5% compared to traditional LEACH protocols. Furthermore, the network lifetime is extended by approximately 340 rounds of transmission under a standard 100-node topology. Statistical evaluation via ANOVA confirms the significance of our optimization model with a p-value less than 0.05. The protocol ensures balanced load distribution, preventing early node death in high-traffic zones. We conclude that integrating GA into hierarchical routing provides a robust solution for long-term environmental monitoring applications where battery replacement is impractical.

Keywords: Wireless Sensor Networks, Genetic Algorithms, Energy Efficiency, Cluster Head Selection, Routing Protocol, Network Lifetime

Manuscript Timeline: Received: November 12, 2008; Revised: December 20, 2008; Accepted: January 15, 2009; Published: February 5, 2009

Citation: Benson, J. A., & Al-Kouri, M. O. (2009). Optimized Energy-Aware Routing Protocol for Wireless Sensor Networks Using Genetic Algorithms. International Journal of Computer Science and Technology, 11(2), 9–16.

International Journal of Computer Science and Technology | Vol. 11, No. 1, January 2009 | pp. 1–8

DOI: 10.46882/2009/IJCST/111022

Research Article

Title: An Automated Vulnerability Assessment Engine for Web Applications Using Fuzz Testing Techniques

Names of Authors: Oliver T. Vance¹, Jessica L. Harper¹

Authors’ Affiliations: ¹School of Computing and Information Systems, University of Melbourne, Melbourne, Australia

Abstract: Web application security is a primary concern for modern e-commerce and banking infrastructures, as injection vulnerabilities consistently expose sensitive backend databases to exploitation. This paper presents an automated, black-box vulnerability assessment engine, named SecureFuzz, designed to detect SQL Injection (SQLi) and Cross-Site Scripting (XSS) anomalies. SecureFuzz operates by dynamically parsing target web page forms, generating malformed input payloads via mutated regular expressions, and analyzing HTTP response statuses and DOM modifications. The engine introduces an intelligent seed selection heuristic that mutates payloads based on the input field text attributes. SecureFuzz was benchmarked across 35 deliberate production web application testbeds. The engine achieved a vulnerability detection recall rate of 94.2% while maintaining a low false-positive declaration rate of 4.3% ± 0.8%. Computational runtimes averaged 1.2 seconds per entry form, presenting security engineering teams with an efficient pipeline asset to audit application security postures prior to release.

Keywords: Web security, fuzz testing, SQL injection, cross-site scripting, vulnerability assessment, automated testing

Manuscript Timeline: Received October 12, 2008; Revised November 25, 2008; Accepted December 15, 2008; Published January 7, 2009

Citation: Vance, O. T., & Harper, J. L. (2009). An Automated Vulnerability Assessment Engine for Web Applications Using Fuzz Testing Techniques. International Journal of Computer Science and Technology, 11(1), 1–8.

International Journal of Computer Science and Technology | Vol. 10, No. 12, December 2008 | pp. 89–96

DOI: 10.46882/2008/IJCST/101221

Research Article

Title: Cross-Layer Design Optimization for Quality of Service Enhancement in IEEE 802.11 Wireless Mesh Networks

Names of Authors: Youssef A. Mansour¹, Fatima Z. Al-Alawi¹

Authors’ Affiliations: ¹Department of Electrical and Computer Engineering, Sultan Qaboos University, Muscat, Oman

Abstract: Wireless Mesh Networks (WMNs) based on the standard IEEE 802.11 architecture face deployment limitations in urban centers due to packet collisions, link degradation, and unfair medium access allocations. Traditional decoupled network layers prevent transmission parameters from adapting to real-time channel dynamics. This research proposes a cross-layer design framework that optimizes interactions between the Medium Access Control (MAC) and network routing layers. The architecture introduces a Channel-Aware Dynamic Contention Window (CADC) algorithm that adjusts backoff parameters based on real-time bit error rates (BER) and routing queue lengths. Simultaneously, the routing protocol selects paths using a hybrid Expected Transmission Time (ETT) metric. Network simulations run via NS-2 showed that this cross-layer approach increased total throughput by 31.4% and minimized end-to-end delay variances down to 14.5 ± 2.1 milliseconds under heavily loaded scenarios. The packet drop ratio decreased by an average of 18.2%, ensuring high Quality of Service (QoS) delivery for real-time traffic profiles.

Keywords: Wireless mesh networks, cross-layer design, Quality of Service, MAC layer optimization, routing metrics, NS-2 simulation

Manuscript Timeline: Received September 10, 2008; Revised October 24, 2008; Accepted November 19, 2008; Published December 12, 2008

Citation: Mansour, Y. A., & Al-Alawi, F. Z. (2008). Cross-Layer Design Optimization for Quality of Service Enhancement in IEEE 802.11 Wireless Mesh Networks. International Journal of Computer Science and Technology, 10(12), 89–96.

International Journal of Computer Science and Technology | Vol. 10, No. 11, November 2008 | pp. 81–88

DOI: 10.46882/2008/IJCST/101120

Research Article

Title: A Hybrid Cryptosystem for Securing Telemedicine Data Transmission Over Public Networks

Names of Authors: Chidi E. Okafor¹, Blessing N. Nwachukwu²

Authors’ Affiliations: ¹Department of Computer Science, University of Nigeria, Nsukka, Nigeria; ²Department of Biomedical Engineering, Federal University of Technology, Owerri, Nigeria

Abstract: Telemedicine applications transmit highly confidential patient health records and diagnostics across open communication channels, creating security risks regarding data intercept and identity theft. This paper details a hybrid cryptographic architecture that secures electronic health records (EHR) and high-resolution medical imagery. The data payloads are encrypted using the Advanced Encryption Standard (AES) with a 256-bit key operating in Cipher Block Chaining (CBC) mode. The ephemeral symmetric AES session keys are concurrently secured using 2048-bit RSA public-key cryptography to enable secure key exchange. Integrity and non-repudiation are verified by appending an SHA-256 digital signature to each transaction packet. Performance profiling showed that the hybrid cryptosystem processes an 8.5 MB MRI image scan within 245 milliseconds on client-side terminals. The encryption process altered data entropy values up to a nearly ideal factor of 7.998 ± 0.001, indicating resilience against statistical cryptanalysis attacks while maintaining compliance with healthcare data privacy mandates.

Keywords: Telemedicine security, hybrid cryptosystem, AES encryption, RSA algorithm, digital signature, medical data privacy

Manuscript Timeline: Received August 5, 2008; Revised September 18, 2008; Accepted October 10, 2008; Published November 4, 2008

Citation: Okafor, C. E., & Nwachukwu, B. N. (2008). A Hybrid Cryptosystem for Securing Telemedicine Data Transmission Over Public Networks. International Journal of Computer Science and Technology, 10(11), 81–88.

International Journal of Computer Science and Technology | Vol. 10, No. 10, October 2008 | pp. 73–80

DOI: 10.46882/2008/IJCST/101019

Research Article

Title: An Automated Regression Testing Framework for Microservices Architecture Software

Names of Authors: Hans-Werner Schmidt¹, Klaus M. Müller¹

Authors’ Affiliations: ¹Institute of Software Technology, Technical University of Munich, Munich, Germany

Abstract: Software development paradigms have moved toward decoupled microservice architectures, presenting challenges for automated QA regression testing due to complex distributed dependencies. Traditional monolithic test automation systems struggle to isolate integration faults when continuous deployment pipelines update microservices independently. This paper introduces an automated regression testing framework tailored for microservice systems, relying on dynamic consumer-driven contract testing. The framework intercepts inter-service RESTful API communication, generating lightweight mock test stubs that simulate service behavior without deploying the entire application stack. Testing trials on an enterprise e-commerce platform with 24 individual microservices demonstrated that the contract-driven framework reduced total test suite execution times by 68.4% compared to end-to-end integration tests. The automated test engine maintained a software defect detection sensitivity of 91.5% ± 1.1%, while lowering false-negative pipeline disruptions down to a baseline rate of 0.5%.

Keywords: Regression testing, microservices, contract testing, continuous integration, test automation, software architecture

Manuscript Timeline: Received July 14, 2008; Revised August 26, 2008; Accepted September 15, 2008; Published October 8, 2008

Citation: Schmidt, H. W., & Müller, K. M. (2008). An Automated Regression Testing Framework for Microservices Architecture Software. International Journal of Computer Science and Technology, 10(10), 73–80.

International Journal of Computer Science and Technology | Vol. 10, No. 9, September 2008 | pp. 65–72

DOI: 10.46882/2008/IJCST/109018

Research Article

Title: Optimizing Hardware Resource Utilization in FPGA Implementations of the Advanced Encryption Standard

Names of Authors: Pierre-Yves Laurent¹, Jean-Luc Moreau¹

Authors’ Affiliations: ¹Laboratory of Microelectronics and Embedded Systems, University of Rennes, Rennes, France

Abstract: Cryptographic security modules embedded within mobile electronic hardware and smart devices demand both high computational throughput and ultra-low power consumption. This paper details an optimized Field Programmable Gate Array (FPGA) implementation of the 128-bit Advanced Encryption Standard (AES) designed to minimize resource utilization while maintaining high processing speeds. The architecture reduces physical gate counts by executing a loop-unrolled pipelined structure where the complex SubBytes and InvSubBytes transformations are mapped to highly efficient block RAM (BRAM) lookup components instead of combinational logic slices. The complete cryptographic core was implemented on a Xilinx Spartan-3 chip environment. Hardware laboratory tests indicated that the core utilized only 412 logic slices and 4 BRAM blocks, achieving a hardware resource reduction of 28.5% compared to baseline iterative architectures. The design achieved a stable data encryption throughput rate of 1.42 Gbps at a maximum operating clock frequency of 118.5 MHz, exhibiting an optimal performance profile for constrained electronic environments.

Keywords: AES encryption, FPGA hardware, hardware optimization, block RAM, cryptography, pipelined architecture

Manuscript Timeline: Received June 18, 2008; Revised July 30, 2008; Accepted August 21, 2008; Published September 9, 2008

Citation: Laurent, P. Y., & Moreau, J. L. (2008). Optimizing Hardware Resource Utilization in FPGA Implementations of the Advanced Encryption Standard. International Journal of Computer Science and Technology, 10(9), 65–72.