International Journal of Computer Science and Technology

International Journal of Computer Science and Technology | Vol. 8, No. 1, January 2006 | pp. 1–8

DOI: 10.46882/2006/IJCST/080116

Research Article

Title: Holistic Schema Matching in Large-Scale XML Repositories Using Semantic Similarity Measures

Names of Authors: Jean-Luc Moreau¹, Yukihiro Sato²

Authors’ Affiliations: ¹Laboratoire d'Informatique Graphique, Université de Lyon, Lyon, France; ²Department of Information Science, Kyoto University, Kyoto, Japan

Abstract:
Integrating structural data across heterogeneous web repositories requires mapping schemas that use different naming conventions and hierarchical designs. This paper develops a holistic schema matching framework for XML documents that analyzes both element labels and contextual data structures. The system computes semantic similarity scores by mapping element terms onto WordNet taxonomies, while structural constraints are evaluated using a modified tree-edit distance algorithm. The framework was evaluated against a benchmark dataset of 50 enterprise XML schemas from the e-commerce sector. The proposed matcher achieved an overall precision rating of P = 89.2% and an F-measure score of 86.5%, outperforming baseline linguistic matchers by 14.8%. The runtime execution complexity was successfully restricted to O(N²) relative to tree node density. This reduction allows the system to discover complex data correspondences in large enterprise data warehouses without requiring extensive manual corrections.

Keywords: Schema Matching, XML Databases, Semantic Web, Data Integration, WordNet Taxonomy

Manuscript Timeline: Received October 12, 2005; Revised November 28, 2005; Accepted December 18, 2005; Published January 24, 2006

Citation: Moreau, J. L., & Sato, Y. (2006). Holistic Schema Matching in Large-Scale XML Repositories Using Semantic Similarity Measures. International Journal of Computer Science and Technology, 8(1), 1–8.

International Journal of Computer Science and Technology | Vol. 7, No. 12, December 2005 | pp. 89–96

DOI: 10.46882/2005/IJCST/071215

Research Article

Title: A Fuzzy Logic Expert System for the Early Diagnosis of Cardiovascular Disorders

Names of Authors: Santiago Ortiz¹, Nneka Okoye²

Authors’ Affiliations: ¹Facultad de Medicina, Universidad de Buenos Aires, Buenos Aires, Argentina; ²Department of Computer Science, University of Ibadan, Ibadan, Nigeria

Abstract:
Developing clinical decision support systems is essential to aid medical practitioners in interpreting complex, multi-variate diagnostic profiles. This study introduces an automated clinical expert system based on fuzzy logic principles for the early risk stratification of cardiovascular disorders. The inference engine processes eleven physiological inputs, including blood pressure readings, serum cholesterol levels, maximum heart rate, and electrocardiogram (ECG) ST-segment depressions. Membership functions map these raw values into linguistic variables, which are then parsed through a rule base of 45 expert-validated conditions. Testing was conducted on a clinical dataset of 303 patient profiles. The fuzzy system achieved a diagnostic sensitivity of 92.4% and a specificity index of 89.1%. Defuzzification tasks, performed using the centroid method, yielded a crisp risk percentage within t = 8 ms. This fast processing time confirms that the system can be deployed on low-cost computing terminals in rural health centers.

Keywords: Fuzzy Logic, Expert Systems, Cardiovascular Diagnosis, Decision Support Systems, Medical Informatics

Manuscript Timeline: Received September 04, 2005; Revised October 20, 2005; Accepted November 11, 2005; Published December 27, 2005

Citation: Ortiz, S., & Okoye, N. (2005). A Fuzzy Logic Expert System for the Early Diagnosis of Cardiovascular Disorders. International Journal of Computer Science and Technology, 7(12), 89–96.

International Journal of Computer Science and Technology | Vol. 7, No. 11, November 2005 | pp. 81–88

DOI: 10.46882/2005/IJCST/071114

Research Article

Title: Hardware Acceleration of the Advanced Encryption Standard on Field Programmable Gate Arrays

Names of Authors: Klaus Meyer¹, Priya Nair²

Authors’ Affiliations: ¹Institute for Computer Engineering, University of Heidelberg, Heidelberg, Germany; ²Department of Electronics Engineering, Cochin University of Science and Technology, Kochi, India

Abstract:
Software implementations of complex symmetric ciphers often introduce throughput bottlenecks in high-speed network gateways. This paper evaluates an optimized hardware architecture for the Advanced Encryption Standard (AES) with a 128-bit key size on Field Programmable Gate Arrays (FPGAs). The proposed core achieves high performance by unrolling the internal cipher loop and using a fully pipelined structure divided into four inner stages. S-box operations are mapped onto dedicated on-chip block RAM units to bypass combinational logic path delays. The design was synthesized on a Xilinx Virtex-4 FPGA device, utilizing 2,450 look-up tables (LUTs) and 10 block RAMs. Operating at a maximum clock frequency of f = 285 MHz, the hardware accelerator achieved a steady-state encryption throughput of 36.48 Gbps. This performance baseline represents a 42.5% speedup over conventional loop-iterative hardware architectures, making it suitable for line-rate bulk encryption in Gigabit Ethernet networks.

Keywords: Hardware Acceleration, Advanced Encryption Standard, FPGA, Pipelined Architecture, Cryptography

Manuscript Timeline: Received August 11, 2005; Revised September 24, 2005; Accepted October 15, 2005; Published November 22, 2005

Citation: Meyer, K., & Nair, P. (2005). Hardware Acceleration of the Advanced Encryption Standard on Field Programmable Gate Arrays. International Journal of Computer Science and Technology, 7(11), 81–88.

International Journal of Computer Science and Technology | Vol. 7, No. 10, October 2005 | pp. 73–80

DOI: 10.46882/2005/IJCST/071013

Research Article

Title: Robust Digital Image Watermarking Using Discrete Wavelet Transform and Singular Value Decomposition

Names of Authors: Chong-Min Wang¹, Aisha Bello²

Authors’ Affiliations: ¹Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan; ²Department of Mathematics and Computer Science, Federal University of Technology, Minna, Nigeria

Abstract:
Protecting digital copyright ownership requires robust watermarking techniques that can withstand aggressive signal-processing attacks without degrading the structural quality of the host image. This paper presents a hybrid digital image watermarking algorithm that combines the multi-resolution analysis of the Discrete Wavelet Transform (DWT) with the stability of Singular Value Decomposition (SVD). The host image is decomposed into four subbands using a first-level DWT, and the singular values of the high-frequency subband (HH) are altered to embed the watermark data. Experimental evaluations on standard 512 x 512 grayscale images demonstrated a peak signal-to-noise ratio (PSNR) of 42.15 dB ± 0.45 dB, showing high imperceptibility. Under aggressive attacks including JPEG compression down to a 10% quality factor, Gaussian noise introduction (variance = 0.02), and median filtering, the watermark extraction routine maintained a normalized correlation (NC) coefficient above 0.94. This balance of imperceptibility and robustness proves the system's effectiveness for secure intellectual property management.

Keywords: Digital Watermarking, Discrete Wavelet Transform, Singular Value Decomposition, Image Security, Robustness

Manuscript Timeline: Received July 05, 2005; Revised August 19, 2005; Accepted September 12, 2005; Published October 25, 2005

Citation: Wang, C. M., & Bello, A. (2005). Robust Digital Image Watermarking Using Discrete Wavelet Transform and Singular Value Decomposition. International Journal of Computer Science and Technology, 7(10), 73–80.

International Journal of Computer Science and Technology | Vol. 7, No. 9, September 2005 | pp. 65–72

DOI: 10.46882/2005/IJCST/070912

Research Article

Title: Energy-Aware Task Scheduling in Heterogeneous Mobile Ad-Hoc Networks Using Ant Colony Optimization

Names of Authors: Fatoumata Diallo¹, Diego Silva²

Authors’ Affiliations: ¹Département de Génie Informatique, École Nationale d'Ingénieurs de Bamako, Bamako, Mali; ²Departamento de Engenharia de Computação, Universidade Federal do Rio de Janeiro, Rio de Janeiro, Brazil

Abstract:
Mobile Ad-hoc Networks (MANETs) consist of battery-powered terminal devices that are resource-constrained and highly prone to premature power exhaustion under intense distributed computing workloads. This paper details a novel energy-aware task scheduling architecture that optimizes workload allocation across heterogeneous mobile groups using a modified Ant Colony Optimization (ACO) heuristic. The scheduling algorithm monitors residual battery energy vectors alongside wireless link quality metrics to assign computational sub-tasks dynamically without over-stressing critical routing nodes. Network modeling configurations with node densities varying between 50 and 200 units showed that the energy-aware ACO model extended the overall operational lifespan of the network topology by 26.8% compared to traditional minimum-laxity scheduling methods. The computational throughput rose by 14.3%, and the packet delivery ratio remained resilient above 96.5% even during rapid spatial changes in the network structure, establishing a durable paradigm for ad-hoc grid computations.

Keywords: Mobile Ad-Hoc Networks, Task Scheduling, Ant Colony Optimization, Energy Harvesting, Network Lifetime

Manuscript Timeline: Received June 04, 2005; Revised July 18, 2005; Accepted August 12, 2005; Published September 23, 2005

Citation: Diallo, F., & Silva, D. (2005). Energy-Aware Task Scheduling in Heterogeneous Mobile Ad-Hoc Networks Using Ant Colony Optimization. International Journal of Computer Science and Technology, 7(9), 65–72.

International Journal of Computer Science and Technology | Vol. 7, No. 8, August 2005 | pp. 57–64

DOI: 10.46882/2005/IJCST/070811

Research Article

Title: An Adaptive Edge-Computing Framework for Low-Latency Multimedia Content Delivery Networks

Names of Authors: Kofi Mensah¹, Hiroshi Tanaka²

Authors’ Affiliations: ¹Department of Computer Engineering, Kwame Nkrumah University of Science and Technology, Kumasi, Ghana; ²Department of Information and Communication Engineering, University of Tokyo, Tokyo, Japan

Abstract:
The increasing consumer demand for high-definition streaming media presents substantial bandwidth bottlenecks for legacy centralized content delivery networks (CDNs). This study introduces an adaptive edge-computing framework designed to decentralize caching operations by deploying localized data staging nodes at the network periphery. The distribution engine evaluates real-time client request matrices and uses a proactive prediction model to push popular media blocks during off-peak hours. Simulations were executed using synthetic traffic profiles across a modeled regional network topology with 150 edge cache layers. The experimental data show that the edge framework reduces the core backbone network utilization by 38.4%, while improving the final end-user content delivery latency from t = 142 ms down to an average of t = 34 ms ± 4 ms under highly congested request scenarios. Additionally, the cache hit ratio (CHR) stabilized at a highly efficient index of 92.15%, validating the system's capacity to minimize backhaul congestion and scale smoothly under sudden, high-volume user traffic spikes.

Keywords: Edge Computing, Content Delivery Networks, Cache Optimization, Low Latency, Multimedia Streaming

Manuscript Timeline: Received May 10, 2005; Revised June 22, 2005; Accepted July 14, 2005; Published August 26, 2005

Citation: Mensah, K., & Tanaka, H. (2005). An Adaptive Edge-Computing Framework for Low-Latency Multimedia Content Delivery Networks. International Journal of Computer Science and Technology, 7(8), 57–64.