International Journal of Computer Science and Technology

International Journal of Computer Science and Technology | Vol. 6, No. 1, January 2004 | pp. 1–8

DOI: 10.46882/2004/IJCST/000054

Article Type: Original Research Paper

Title: A Highly Scalable Peer-to-Peer Grid Computing Architecture for Distributed Data Mining

Names of Authors: John A. Benson¹, Ananya Rao²

Authors’ Affiliations: ¹Department of Computer Science, University of Technology, London, UK; ²School of Data Science, Tech-Institute of Bangalore, Karnataka, India

Abstract: Distributed data mining over large-scale wide-area networks requires significant computational infrastructure and robust communication protocols. This paper presents a decentralized Peer-to-Peer (P2P) grid computing architecture designed to execute complex association rule mining without relying on a centralized coordinator. The system introduces a dynamic topology balancing protocol that group nodes based on their available bandwidth and processing power. We implement a non-blocking communication layout using universal text streams to coordinate local frequent itemset exchanges across active nodes. Simulation benchmarks involving 5000 virtual nodes demonstrated that our P2P model achieves a 22.4% reduction in global bandwidth usage compared to traditional master-slave grid frameworks. Furthermore, the computation throughput scaled near-linearly at an efficiency rating of 89.2 ± 1.5%, demonstrating high stability for large-scale data analysis across globally distributed environments.

Keywords: Peer-to-Peer Networks, Grid Computing, Distributed Data Mining, Association Rules, Load Balancing

Manuscript Timeline: Received: October 14, 2003; Revised: November 28, 2003; Accepted: December 20, 2003; Published: January 08, 2004

Citation: Benson, J. A., & Rao, A. (2004). A Highly Scalable Peer-to-Peer Grid Computing Architecture for Distributed Data Mining. International Journal of Computer Science and Technology, 6(1), 1–8.

International Journal of Computer Science and Technology | Vol. 5, No. 13, Special Issue 2003 | pp. 97–104

DOI: 10.46882/2003/IJCST/000053

Article Type: Research Article

Title: Performance Evaluation of TCP Congestion Control Mechanisms over High-Speed Satellite Links

Names of Authors: Samuel Kwesi¹, Jean-Claude Mpasa²

Authors’ Affiliations: ¹Department of Computer Engineering, Kwame Nkrumah University of Science and Technology, Kumasi, Ghana; ²Department of Computer Science, University of Kinshasa, Democratic Republic of the Congo

Abstract: Standard Transmission Control Protocol (TCP) congestion window mechanics suffer from severe performance degradation when operating across long-delay, asymmetric satellite internet channels. This study presents a comparative empirical evaluation of four network transport protocols—TCP Tahoe, Reno, NewReno, and Vegas—under simulated geostationary satellite conditions. Using an industrial network testbed with a round-trip time (RTT) setting of 540 ms, we measured throughput efficiency and packet loss adaptation trends. The experimental data revealed that TCP Vegas achieved a 16.5% higher link utilization rate than TCP Reno by using proactive queue delay monitoring instead of relying on packet drop events. Our mathematical validation model shows that implementing a selective acknowledgment mechanism (SACK) decreases retransmission overhead by 32.1%. These findings provide a clear guide for optimizing satellite broadband deployments in rural areas lacking wired telecommunications access networks.

Keywords: TCP Congestion Control, Satellite Networks, Transport Protocols, Throughput Optimization, Performance Evaluation

Manuscript Timeline: Received: September 05, 2003; Revised: November 02, 2003; Accepted: November 29, 2003; Published: December 28, 2003

Citation: Kwesi, S., & Mpasa, J.-C. (2003). Performance Evaluation of TCP Congestion Control Mechanisms over High-Speed Satellite Links. International Journal of Computer Science and Technology, 5(13), 97–104.

International Journal of Computer Science and Technology | Vol. 5, No. 12, December 2003 | pp. 89–96

DOI: 10.46882/2003/IJCST/000052

Article Type: Original Research Paper

Title: An Intelligent Context-Aware Agent Architecture for Personalized Mobile Commerce Applications

Names of Authors: Marcello Rossi¹, Amina Bekele²

Authors’ Affiliations: ¹Department of Automation Engineering, University of Bologna, Italy; ²Department of Information Science, Addis Ababa University, Ethiopia

Abstract: The growing adoption of wireless handheld devices creates new opportunities for personalized mobile commerce, yet delivering relevant, timely service matches remains problematic due to limited display sizes. This paper presents an intelligent context-aware multi-agent architecture designed to push tailored product recommendations directly to mobile shoppers. The engine parses user demographic records, current GPS location parameters, and real-time local weather profiles to dynamically construct individualized preference trees. Field experiments involving 200 active users demonstrated that our personalization model yielded a 22.4% higher click-through conversion rate compared to non-contextual advertising networks. The runtime tracking system processes complex contextual rules in under 18 ms, minimizing processing demands on embedded mobile hardware platforms. This framework sets a blueprint for modern location-based marketing tools.

Keywords: Mobile Commerce, Multi-Agent Systems, Context-Aware Computing, Personalization Engines, Location-Based Services

Manuscript Timeline: Received: August 18, 2003; Revised: October 14, 2003; Accepted: November 11, 2003; Published: December 12, 2003

Citation: Rossi, M., & Bekele, A. (2003). An Intelligent Context-Aware Agent Architecture for Personalized Mobile Commerce Applications. International Journal of Computer Science and Technology, 5(12), 89–96.

International Journal of Computer Science and Technology | Vol. 5, No. 11, November 2003 | pp. 81–88

DOI: 10.46882/2003/IJCST/000051

Article Type: Research Article

Title: An Evolutionary Clustering Algorithm for Optimal Sensor Placement in Wireless Ad-Hoc Networks

Names of Authors: Liam O'Connor¹, Fatima Al-Suwaidi²

Authors’ Affiliations: ¹School of Computer Science, Trinity College Dublin, Ireland; ²Department of Electrical Engineering, United Arab Emirates University, Al Ain, UAE

Abstract: Wireless ad-hoc sensor networks are constrained by limited individual node batteries and unstable radio transmission spaces, requiring optimal layout planning to extend system lifetimes. This paper proposes an Evolutionary Cluster-Head Selection (ECHS) protocol built upon an optimized Particle Swarm Optimization (PSO) routine. ECHS dynamically designates cluster nodes by combining geographic positioning data, radio propagation variables, and individual residual energy metrics. Network simulations conducted using an NS-2 matrix across a 500 node grid showed that ECHS extended the operational time before the first node died by 28.6% compared to classical LEACH protocols. The data delivery success rate stayed above 94.2% under high packet traffic conditions. Furthermore, the overall routing protocol traffic overhead was minimized by 15.3%, offering an industrial solution for long-term ecological and environmental tracking frameworks.

Keywords: Wireless Sensor Networks, Clustering Protocols, Particle Swarm Optimization, Energy Efficiency, Network Lifecycle

Manuscript Timeline: Received: July 20, 2003; Revised: September 12, 2003; Accepted: October 10, 2003; Published: November 05, 2003

Citation: O'Connor, L., & Al-Suwaidi, F. (2003). An Evolutionary Clustering Algorithm for Optimal Sensor Placement in Wireless Ad-Hoc Networks. International Journal of Computer Science and Technology, 5(11), 81–88.

International Journal of Computer Science and Technology | Vol. 5, No. 10, October 2003 | pp. 73–80

DOI: 10.46882/2003/IJCST/000050

Article Type: Original Research Paper

Title: An Object-Oriented Framework for Automated Refactoring of Legacy Procedural Source Code

Names of Authors: John A. Benson¹, Ananya Rao²

Authors’ Affiliations: ¹Department of Computer Science, University of Technology, London, UK; ²School of Data Science, Tech-Institute of Bangalore, Karnataka, India

Abstract: Software maintainability remains an expensive challenge for corporate entities operating massive legacy systems written in procedural development languages. This paper introduces an automated migration framework designed to parse procedural code bases and refactor them into structured object-oriented software patterns. The system relies on a structural Abstract Syntax Tree (AST) analyzer that identifies functional dependencies, data groupings, and global state variables. These procedural clusters are systematically mapped into standalone classes by optimizing cohesive coupling indicators. We validated the tool on an industrial library containing 150,000 lines of legacy C source code, translating it directly into functional C++ structures. Quantitative evaluation metrics showed a 34.5% reduction in cyclomatic complexity indexes. Software engineers corroborated these metrics, reporting a significant improvement in manual debugging speed and code legibility across the migrated system architecture.

Keywords: Software Refactoring, Object-Oriented Frameworks, Legacy Systems, Abstract Syntax Trees, Structural Metrics

Manuscript Timeline: Received: June 15, 2003; Revised: August 04, 2003; Accepted: September 02, 2003; Published: October 19, 2003

Citation: Benson, J. A., & Rao, A. (2003). An Object-Oriented Framework for Automated Refactoring of Legacy Procedural Source Code. International Journal of Computer Science and Technology, 5(10), 73–80.

International Journal of Computer Science and Technology | Vol. 5, No. 9, September 2003 | pp. 65–72

DOI: 10.46882/2003/IJCST/000049

Article Type: Research Article

Title: Design and Implementation of a Secure Cryptographic Coprocessor for Embedded Smart Card Systems

Names of Authors: Sophie Dubois¹, Hans-Werner Schmidt²

Authors’ Affiliations: ¹Department of Applied Cryptography, ENS Paris, France; ²Fraunhofer Institute for Secure Information Technology, Darmstadt, Germany

Abstract: Embedded electronic banking and identity assets are increasingly vulnerable to hardware physical tampering and non-invasive side-channel monitoring. This paper details the microarchitecture design of a high-speed cryptographic coprocessor optimized for smart card IC hardware configurations. The processing core features a hardware-based Montgomery multiplication accelerator that executes 1024-bit modular exponentiation instructions for RSA operations in under 4.8 ms. To counter differential power analysis (DPA) attacks, we incorporate randomized dummy state insertions and balanced dual-rail logic layout constraints into the ALU. Prototype hardware verification on an ASIC layout demonstrated a maximum operating frequency of 33 MHz while drawing a low current profile of 2.4 mA at 3.3 V. The entire design occupies less than 0.85 mm² of silicon area, meeting the strict power constraints required for deployment in international financial transaction terminals.

Keywords: Cryptographic Hardware, Smart Cards, Embedded Security, Side-Channel Attacks, Montgomery Multiplication, ASIC Design

Manuscript Timeline: Received: May 12, 2003; Revised: July 01, 2003; Accepted: July 28, 2003; Published: September 10, 2003

Citation: Dubois, S., & Schmidt, H.-W. (2003). Design and Implementation of a Secure Cryptographic Coprocessor for Embedded Smart Card Systems. International Journal of Computer Science and Technology, 5(9), 65–72.